TTTC: DFM&Y 2011 Call for Papers - Submission Deadline Extended to April 11th!

Submission Deadline Extended to April 11, 2011!

CALL FOR PAPERS

Scope -- Submissions -- Key Dates -- Additional Information -- Committees

Scope

Increased manufacturing variability in leading-edge process technologies requires new paradigms and solution technologies for yield optimization. SoC manufacturability and yield entails design- specific optimization of the manufacturing, and thus enhanced communications across the design-manufacturing interface. A wide range of Design-for-Manufacturability (DFM) and Design-for-Yield (DFY) methodologies and tools has been proposed in recent years. Some of these tools are leveraged during back-end design, others are applied just before manufacturing handoff, and still others are applied post-design, from reticle enhancement and lithography through wafer sort, packaging, final test and failure analysis. DFM and DFY can dramatically impact the business performance of chip manufacturers. It can also significantly affect age-old chip design flows. Using DFM and DFY solutions is an investment, and choosing the most cost effective one(s) requires careful analysis of integration and schedule overheads, versus quantified benefits. This workshop analyzes this key trend and its challenges, and provides an opportunity to discuss a range of DFM and DFY solutions for today’s SoC designs.

Representative topics include, but are not limited to:

Electrical, Design-Driven DFM
Built-in Repair Analysis and Self-Repair
Adaptive Design Techniques in DFM/DFY
Embedded Test and Diagnosis
OPC and RET
DFM for 3D Integration
DFM at System/Architecture Level
Analog and Mixed-Signal DFM
Process Monitoring IP
Statistical Design
Test-based Yield Learning
Design-Aware Manufacturing
Yield Enhancement IP
Yield Management

Submissions

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To present at the Workshop, authors are invited to submit unpublished extended abstracts or full papers, 2 to 4 pages in length. Submissions on ambitious works in progress are also encouraged. Each submission should include a short abstract of 50 words, and keywords. The review process is blind. Please do not include author names or affiliations. Proposals for embedded tutorials and panel discussions are also invited. Submit a copy of your paper proposal as a PDF at

http://www.easychair.org/conferences/?conf=dfmy2011

The goal of the workshop is to foster unrestricted discussion in the field of design-manufacturing interactions. Copies of papers will be provided to attendees in the form of Workshop Notes, but no proceedings will be published. Therefore, accepted papers can still be submitted to other conferences and journals.

Submissions are due no later than April 11th, 2011

Authors will be notified of the disposition of their papers by April 25th, 2011. Authors of accepted papers must submit an illustrated text by May 15th, 2011 for inclusion in the Workshop Notes, which will be provided to the attendees.

Key Dates

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Submission deadline: April 11, 2011
Notification of acceptance: April 25, 2011
Final copy deadline: May 15, 2011

Additional Information

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General Chair
R. Aitken, ARM
rob.aitken@arm.com

Committees

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General Chair
R. Aitken, ARM
rob.aitken@arm.com

Program Chair
P. Gupta, UCLA
puneet@ee.ucla.edu

Publicity
J. Lu, UCSD

Steering Committee
A. B. Kahng, UCSD
A. Singh, Auburn Univ.
Y. Zorian, Synopsys

Program Committee
M. Abu-Rahma, Qualcomm
S. Datla, Texas Instruments
A. Gattiker, IBM
P. Gupta, UCLA
S. Gupta, USC
A. B. Kahng, UCSD
V. Moroz, Synopsys
N. S. Nagaraj, Texas Instruments
M. Orshansky, Univ. of Texas
D. Pan, Univ. of Texas
C.-H. Park, Samsung
J.M. Portal, Univ. of Marseilles
T. Quan, TSMC
P. Sharma, Freescale
T. Shibuya, Fujitsu
A. Singhee, IBM
R. Topaloglu, Global Foundries
A. Torres, Mentor Graphics

For more information, visit us on the web at: http://vlsicad.ucsd.edu/DFMY

The 5th IEEE International Workshop on Design for Manufacturability & Yield (DFM&Y 2011) is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC) in cooperation with the IEEE Council on Electronic Design Automation (CEDA).